1. Field of the Invention
The present invention relates to a structure of a reconfigurable processor (RP), and more particularly, to a multi-core processor using a coarse-grained array.
2. Description of the Related Art
A reconfigurable architecture means a circuit in which built-in functions can be changed according to a user's intention. A reconfigurable processor which is used in a system or terminal to operate a mode, for example, a standardized communication mode, a multimedia mode, etc., can be implemented by combining a Very Long Instruction Word (VLIW) processor with a Coarse Grained Array (CGA).
However, in order to provide multiple modes in which various applications operate simultaneously using such a reconfigurable processor, a plurality of reconfigurable processors each including a VLIW processor and a CGA array, corresponding to the number of the modes, have to be provided. However, this configuration makes the hardware of the CGA array complicated, and is disadvantageous when it is applied to a user terminal, etc. which have to have the characteristics of low power consumption and low capacity.